SRAM/ROM Controller IP
TrueSilicon’s SRAM/ROM Controller IP provides chip designers and architects, an efficient way to connect different AMBA protocol based IPs to memories with reduced latency, power, and area Compliant with AMBA 5/4/3 AXI & AHB
Key Benefits
- Available in native verilog (RTL)
- Linting, Synthesis, CDC, RDC are cleaned up.
- 100% Code coverage
- Verified with an expert team using comprehensive and Regression Test Suites
- IP generation tool and programmable model
- Dynamic power saving
- 24X5 customer support
Features
- Support AMBA AXI4 and AHB3-Lite protocol to SRAM interface
- Support back-to-back transfer
- Support back-to-back write and read transfer for AHB interface
- Configurable data width
- Configurable write and read access cycle for external memory
- Error detection mechanism and provide error response
- APB interface for configuring SRAM controller
- Dynamic clock gating for memory
Deliverables
- Controller
- Master interface - AXI/AHB
- Slave interface - SRAM/ROM
- IP generator & configuration tool
- Verilog test environment with verilog testcases
- IP analysis reports
- Linting report
- Synthesis report
- IP-XACT RDL generated address map
- Simulation script
- IP Block Guide
- Quick Start Guide
